• Perform spice simulation based circuit checks for design robustness, and to validate performance change
• Help automate and enhance standard cell design model generation and QA, including optimization required in mapping to new technology
• Develop new checks to strengthen stdcell design QA checks

Requirement:

• Bachelor/Master Degree in Electrical Engineering
• Minimum 1 year of standard cell or ASIC design experience.
• Understanding of spice netlist and extracted DSPF formats
• Familiarity with common standard cell functionality
• Knowledge of CMOS device physics and technology
• Experience in writing checks using scripting languages in perl, tcl
• Knowledge of hspice and similar circuit simulators
• Experience in digital implementation design using Synthesis and P&R a plus

Yvonne Ong EA License No.: 02C3423 Personnel Registration No.: R1549551

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