Senior DFT Engineer (Design For Test/ Semiconductor)

Location Singapore
Discipline Information & Communications Technology
Job Reference BBBH100912_1655806486
Salary S$6000 - S$7000 per month + VB
Consultant Name Teh Hui Tian, Zoe
Consultant Email
Consultant Contact No. 6232 5252
EA License No. 02C3423
Consultant Registration No. R2089915


  • Advance Structural Test Patterns for multiple IPs
  • Accountable for target Structural test coverage for Digital logic, SRAMs and Mixed-Signal IPs
  • Design FPGA Logic to apply test patterns and improve the diagnostic capability
  • Scan/iJTAG/Memory BIST flow development, ATPG pattern generation, verification, and coverage analysis
  • Pre-silicon verification of DFT schemes and patterns using Industry standard tools
  • Diagnose and debug the pattern failures on ATE to root cause the problem
  • Work with Design Team and Product Engineering Teams to meet production schedule


  • Master's or Bachelor degree in Electronics and Communications Engineering or equivalent
  • 2 to 5 years of working experience in DFT and ATPG
  • Knowledge of Fault modelling, Scan architecture, Scan compression and Memory testing techniques
  • Expertise with industry standard tools like TestKompress, DFT advisor, DFT Compiler
  • Experience in Gate Level Simulation and Debug
  • Good knowledge of Digital design and ASIC design flow
  • Good Knowledge of Verilog/ VHDL
  • Knowledge of Shel Scripting/ Perl/ C++ is a plus

Teh Hui Tian, Zoe EA License No. 02C3423 Personnel Registration No. R2089915

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