Responsibilities:

• Develop script to create Verilog/VHDL netlist (RTL or structure HDL)
• Develop automated systems for silicon test patterns generation of SOC designs
• Develop tools to analyse simulated circuit behaviours at different levels
• Work with test development for functional and structural test to improve test generation flow
• Enhance existing FPGA synthesis and implementation flows
• Invent automated tool for post-silicon validation test sequence that works across test methods and hardware test platforms
• Debug complex pre and post silicon issues that require a blend of Software and Hardware skills

Requirements:

• BS or MS in Computer Science/Software Engineering/Electrical Engineering
• 2-5 years of experience in engineering tools development
• Well-versed in scripting languages including Perl, Python and TCL
• Knowledge of structural or functional verification methodologies is a plus
• Familiar with test methods and hardware test platforms e.g., bench system board and Automatic Test Equipment (ATE) is a plus

Teh Hui Tian, Zoe EA License No. 02C3423 Personnel Registration No. R2089915

Please note that your response to this advertisement and communications with us pursuant to this advertisement will constitute informed consent to the collection, use and/or disclosure of personal data by ManpowerGroup Singapore for the purpose of carrying out its business, in compliance with the relevant provisions of the Personal Data Protection Act 2012. To learn more about ManpowerGroup's Global Privacy Policy, please visit https://www.manpower.com.sg/privacy-policy